JEDEC STANDARD Test Method for Real-Time Soft Error Rate JESD89-1B Addendum No. 1 to JESD89 (RevisionofJESD89-1A,October2007) JULY 2021 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION JEDEC NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and subsequently reviewed and approved by the JEDEC legal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adoption may involve patents or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications The information included in JEDEC standards and publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an ANSI standard. No claims to be in conformance with this standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or call (703) 907-7559 or www.jedec.org Published by @JEDEC Solid State Technology Association 2021 2500 Wilson Boulevard Arlington, VA 22201-3834 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or resell the resulting material. PRICE: Please refer to the current Catalog of JEDEC Engineering Standards and Publications online at http://www.jedec.org/Catalog/catalog.cfm Printed in the U.S.A. All rights reserved PLEASE! DON'T VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permission. For information, contact: JEDEC Solid State Technology Association 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information. JEDEC Standard No.89-1B Page 1 TEST METHOD FOR REAL-TIME SOFT ERROR RATE (From JEDEC Board Ballot JCB-20-64, formulated under the cognizance of the JC-14.1 Subcommitee on Reliability Test Metods for Packaged Devices.) 1 Scope This test is used to determine the Soft Error Rate (SER) of solid state volatile memory arrays and bistable logic elements (e.g. flip-flops) for errors which require no more than re-reading or re-writing to correct and as used in terrestrial environments. It simulates the operating condition intended for execution in ambient conditions without the artificial introduction of radiation sources. JEsD89-1 is offered to define concisely the requirements for executing this test in a standardized fashion. It is intended for use in conjunction with JEsD89 which includes background on reasons for these requirements. NOTE 1 Typically, soft error rate characterization by this test method will be executed by the device manufacturer. Other parties may also apply this method appropriately in conjunction with the manufacturer'sproduct datasheet NOTE 2 The term real-time soft-error rate (RTSER) is preferred over the term system soft-error rate (SSER). NOTE 3 Special considerations apply to devices that are more than memory arrays and/or bistable logic elements. These can preclude the application of this test procedure. Refer to JEsD89 for further discussion