论文标题
以最小的硬件成本朝着多重恒定乘法
Towards the Multiple Constant Multiplication at Minimal Hardware Cost
论文作者
论文摘要
多个恒定乘法（MCM）超过整数是在需要高度优化硬件的嵌入式系统中出现的频繁操作。一种有效的方法是将昂贵的通用乘法替换为位移位和添加，即无乘数电路。在这项工作中，我们基于整数线性编程（ILP）改进了MCM的最佳最佳方法。我们基于计算一位添加器的数量，并证明它与LUT计数密切相关，从而引入了新的低级硬件成本。这种无乘数MCM电路的新模型允许我们考虑中间截断，当不需要完整的输出精度时，可以显着节省资源。我们将错误传播规则合并到我们的ILP模型中，以确保在MCM结果上绑定的用户赋予错误。 MCM多种口味的提议的ILP模型被用作开源工具，并与Flopoco Code Generator相结合，提供完整的系数到-VHDL流。我们在广泛的实验中评估了我们的模型，并对设计指标对实际合成硬件的影响进行了深入的分析。
Multiple Constant Multiplication (MCM) over integers is a frequent operation arising in embedded systems that require highly optimized hardware. An efficient way is to replace costly generic multiplication by bit-shifts and additions, i.e. a multiplierless circuit. In this work, we improve the state-of-the-art optimal approach for MCM, based on Integer Linear Programming (ILP). We introduce a new lower-level hardware cost, based on counting the number of one-bit adders and demonstrate that it is strongly correlated with the LUT count. This new model for the multiplierless MCM circuits permitted us to consider intermediate truncations that permit to significantly save resources when a full output precision is not required. We incorporate the error propagation rules into our ILP model to guarantee a user-given error bound on the MCM results. The proposed ILP models for multiple flavors of MCM are implemented as an open-source tool and, combined with the FloPoCo code generator, provide a complete coefficient-to-VHDL flow. We evaluate our models in extensive experiments, and propose an in-depth analysis of the impact that design metrics have on actually synthesized hardware.
