论文标题

多模式空间信号处理器,带有彩虹状快速梁训练和宽带通信,使用真实时间延迟阵列

Multi-Mode Spatial Signal Processor with Rainbow-like Fast Beam Training and Wideband Communications using True-Time-Delay Arrays

论文作者

Lin, Chung-Ching, Puglisi, Chase, Boljanovic, Veljko, Yan, Han, Ghaderi, Erfan, Gaddis, Jayce, Xu, Qiuyan, Poolakkal, Sreeni, Cabric, Danijela, Gupta, Subhanshu

论文摘要

毫米波(MMW)无线的初始访问对于成功实现第五代(5G)无线网络及其他地区至关重要。现有标准的带宽有限,并且在模拟/混合分阶段 - 安特纳纳阵列(PAA)中使用相变的使用者不适用于要求低延迟方向查找的这些新兴标准。这项工作提出了具有频率划分梁训练方法和宽带束平方的基于可重构的真实时间延迟(TTD)的空间信号处理器(SSP)。离散的时间延迟补偿时钟技术用于支持800 〜MHz带宽,并具有较大的统一带宽环形示波器(坡道)基于信号组合仪。为了在不同的SSP模式和频角对上广泛表征所提出的SSP,使用计算机视觉技术开发自动测试床,从而显着加快了测试进度并最大程度地减少可能的人体错误。 TTD SSP使用七个级别的时间间隔,在800 MHz上的延迟范围为3.8 ns,并在光束训练模式下实现了唯一的频率与角度映射,在光束成型模式下,近12 dB频率与频率无关。 SSP在65nm CMO中进行了原型,其面积为1.98mm $^2 $仅消耗29兆瓦,不包括缓冲液。此外,以122.8 Mb/s的速度实现了16 QAM调制的误差矢量幅度(EVM)。

Initial access in millimeter-wave (mmW) wireless is critical toward successful realization of the fifth-generation (5G) wireless networks and beyond. Limited bandwidth in existing standards and use of phase-shifters in analog/hybrid phased-antenna arrays (PAA) are not suited for these emerging standards demanding low-latency direction finding. This work proposes a reconfigurable true-time-delay (TTD) based spatial signal processor (SSP) with frequency-division beam training methodology and wideband beam-squint less data communications. Discrete-time delay compensated clocking technique is used to support 800~MHz bandwidth with a large unity-gain bandwidth ring-amplifier (RAMP)-based signal combiner. To extensively characterize the proposed SSP across different SSP modes and frequency-angle pairs, an automated testbed is developed using computer-vision techniques that significantly speeds up the testing progress and minimize possible human errors. Using seven levels of time-interleaving for each of the 4 antenna elements, the TTD SSP has a delay range of 3.8 ns over 800 MHz and achieves unique frequency-to-angle mapping in the beamtraining mode with nearly 12 dB frequency-independent gain in the beamforming mode. The SSP is prototyped in 65nm CMOS with an area of 1.98mm$^2$ consuming only 29 mW excluding buffers. Further, an error vector magnitude (EVM) of 9.8% is realized for 16-QAM modulation at a speed of 122.8 Mb/s.

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