论文标题
DNN-CHIP预测器：具有各种数据流和硬件体系结构的DNN加速器的分析性能预测指标
DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architectures
论文作者
论文摘要
最近的深神经网络（DNN）的突破刺激了对DNN加速器的需求大大增加。但是，设计DNN加速器的设计通常是数月/年，并且需要跨学科知识。为了实现快速有效的DNN加速器开发，我们提出了DNN-CHIP预测指标，这是一个分析性能预测指标，可以准确预测DNN加速器的能量，吞吐量和潜伏期，然后才能进行实际实施。我们的预测指标具有两个亮点：（1）其DNN ASIC/FPGA加速器的分析性能公式促进了快速设计空间探索和优化； （2）它支持具有不同算法到硬件映射方法（即数据流）和硬件体系结构的DNN加速器。基于2个DNN模型和3种不同ASIC/FPGA实现的实验结果表明，我们的DNN-CHIP预测器的预测性能与FPGA/ASIC实现的芯片测量结果不同，当使用不同的DNN模型，硬件体系结构和数据流时，FPGA/ASIC实现的芯片测量值不超过17.66％。我们将在接受后发布代码。
The recent breakthroughs in deep neural networks (DNNs) have spurred a tremendously increased demand for DNN accelerators. However, designing DNN accelerators is non-trivial as it often takes months/years and requires cross-disciplinary knowledge. To enable fast and effective DNN accelerator development, we propose DNN-Chip Predictor, an analytical performance predictor which can accurately predict DNN accelerators' energy, throughput, and latency prior to their actual implementation. Our Predictor features two highlights: (1) its analytical performance formulation of DNN ASIC/FPGA accelerators facilitates fast design space exploration and optimization; and (2) it supports DNN accelerators with different algorithm-to-hardware mapping methods (i.e., dataflows) and hardware architectures. Experiment results based on 2 DNN models and 3 different ASIC/FPGA implementations show that our DNN-Chip Predictor's predicted performance differs from those of chip measurements of FPGA/ASIC implementation by no more than 17.66% when using different DNN models, hardware architectures, and dataflows. We will release code upon acceptance.
