论文标题
培训使用FPGA逐步对深网进行二进制化网络
Training Progressively Binarizing Deep Networks Using FPGAs
论文作者
论文摘要
虽然针对二进制神经网络（BNN）的推理例程的硬件实现是对有效的BNN硬件训练加速器的当前实现，适用于物联网（IoT）边缘设备，但仍需提供很多需要。常规的BNN硬件训练加速器通过采用二进制表示形式的参数进行前向和向后传播，并使用采用浮动或固定点实现的代表的参数进行优化 - 要求两套不同的网络参数集。在本文中，我们提出了一种适合硬件友好的培训方法，该方法与传统方法相反，逐步将一组单一的定点网络参数二进制，从而显着减少了功率和资源利用。我们使用Intel FPGA SDK进行OpenCL开发环境，在OpenVino FPGA上逐步训练我们的逐步二进制DNN。我们使用CIFAR-10对GPU和FPGA进行训练方法，并将其与常规BNN进行比较。
While hardware implementations of inference routines for Binarized Neural Networks (BNNs) are plentiful, current realizations of efficient BNN hardware training accelerators, suitable for Internet of Things (IoT) edge devices, leave much to be desired. Conventional BNN hardware training accelerators perform forward and backward propagations with parameters adopting binary representations, and optimization using parameters adopting floating or fixed-point real-valued representations--requiring two distinct sets of network parameters. In this paper, we propose a hardware-friendly training method that, contrary to conventional methods, progressively binarizes a singular set of fixed-point network parameters, yielding notable reductions in power and resource utilizations. We use the Intel FPGA SDK for OpenCL development environment to train our progressively binarizing DNNs on an OpenVINO FPGA. We benchmark our training approach on both GPUs and FPGAs using CIFAR-10 and compare it to conventional BNNs.
